diff --git a/docs/register-map-c1.json b/docs/register-map-c1.json
index ebe0ed4..841a8d5 100644
--- a/docs/register-map-c1.json
+++ b/docs/register-map-c1.json
@@ -1,9 +1,9 @@
 {
   "controller": "C1",
-  "report_generated": "2026-06-18",
+  "report_generated": "2026-06-19",
   "float_format": "FP_B",
   "notes": "Register map built from Sinam_Tag_all.xlsx (C1 only). Experion point names are keys; .MD reads LoopStatus(0xBE) and writes AutoManState(0xBA). archive flag indicates history target.",
-  "register_count": 1086,
+  "register_count": 1089,
   "registers": [
     {
       "tag": "FICQ-111.PV",
@@ -6075,6 +6075,16 @@
       "description": "LOOP #13 Gain1",
       "archive": false
     },
+    {
+      "tag": "LICA-705.GAIN",
+      "addr": 3148,
+      "write_addr": 3148,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux GAIN",
+      "archive": false
+    },
     {
       "tag": "LICA-123.Direction",
       "addr": 3150,
@@ -6095,6 +6105,16 @@
       "description": "LOOP #13 Reset1",
       "archive": false
     },
+    {
+      "tag": "LICA-705.RESET",
+      "addr": 3152,
+      "write_addr": 3152,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RESET",
+      "archive": false
+    },
     {
       "tag": "LICA-123.RATE",
       "addr": 3154,
@@ -6105,6 +6125,16 @@
       "description": "LOOP #13 Rate1",
       "archive": false
     },
+    {
+      "tag": "LICA-705.RATE",
+      "addr": 3154,
+      "write_addr": 3154,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RATE",
+      "archive": false
+    },
     {
       "tag": "LICA-123.CycleTime1",
       "addr": 3156,
diff --git a/docs/register-map-c2.json b/docs/register-map-c2.json
index ee3edf9..4db50e5 100644
--- a/docs/register-map-c2.json
+++ b/docs/register-map-c2.json
@@ -1,9 +1,9 @@
 {
   "controller": "C2",
-  "report_generated": "2026-06-18",
+  "report_generated": "2026-06-19",
   "float_format": "FP_B",
   "notes": "Register map built from Sinam_Tag_all.xlsx (C2 only). Experion point names are keys; .MD reads LoopStatus(0xBE) and writes AutoManState(0xBA). archive flag indicates history target.",
-  "register_count": 1545,
+  "register_count": 1548,
   "registers": [
     {
       "tag": "FICQ-2111.PV",
@@ -7585,6 +7585,16 @@
       "description": "LOOP #16 Gain1",
       "archive": false
     },
+    {
+      "tag": "LICA-2705.GAIN",
+      "addr": 3916,
+      "write_addr": 3916,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux GAIN",
+      "archive": false
+    },
     {
       "tag": "LICA-2111.Direction",
       "addr": 3918,
@@ -7605,6 +7615,16 @@
       "description": "LOOP #16 Reset1",
       "archive": false
     },
+    {
+      "tag": "LICA-2705.RESET",
+      "addr": 3920,
+      "write_addr": 3920,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RESET",
+      "archive": false
+    },
     {
       "tag": "LICA-2111.RATE",
       "addr": 3922,
@@ -7615,6 +7635,16 @@
       "description": "LOOP #16 Rate1",
       "archive": false
     },
+    {
+      "tag": "LICA-2705.RATE",
+      "addr": 3922,
+      "write_addr": 3922,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RATE",
+      "archive": false
+    },
     {
       "tag": "LICA-2111.CycleTime1",
       "addr": 3924,
diff --git a/docs/register-map-c3.json b/docs/register-map-c3.json
index 6936a89..289eeaf 100644
--- a/docs/register-map-c3.json
+++ b/docs/register-map-c3.json
@@ -1,9 +1,9 @@
 {
   "controller": "C3",
-  "report_generated": "2026-06-18",
+  "report_generated": "2026-06-19",
   "float_format": "FP_B",
   "notes": "Register map built from Sinam_Tag_all.xlsx (C3 only). Experion point names are keys; .MD reads LoopStatus(0xBE) and writes AutoManState(0xBA). archive flag indicates history target.",
-  "register_count": 2155,
+  "register_count": 2161,
   "registers": [
     {
       "tag": "FICQ-8101.PV",
@@ -8545,6 +8545,16 @@
       "description": "LOOP #18 Gain1",
       "archive": false
     },
+    {
+      "tag": "LICA-5113.GAIN",
+      "addr": 4428,
+      "write_addr": 4428,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux GAIN",
+      "archive": false
+    },
     {
       "tag": "PICA-6211.Direction",
       "addr": 4430,
@@ -8565,6 +8575,16 @@
       "description": "LOOP #18 Reset1",
       "archive": false
     },
+    {
+      "tag": "LICA-5113.RESET",
+      "addr": 4432,
+      "write_addr": 4432,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RESET",
+      "archive": false
+    },
     {
       "tag": "PICA-6211.RATE",
       "addr": 4434,
@@ -8575,6 +8595,16 @@
       "description": "LOOP #18 Rate1",
       "archive": false
     },
+    {
+      "tag": "LICA-5113.RATE",
+      "addr": 4434,
+      "write_addr": 4434,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RATE",
+      "archive": false
+    },
     {
       "tag": "PICA-6211.CycleTime1",
       "addr": 4436,
@@ -18005,6 +18035,36 @@
       "description": "LOOP #25 StepMotorTime",
       "archive": false
     },
+    {
+      "tag": "FICQ-8118.GAIN",
+      "addr": 30880,
+      "write_addr": 30880,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux GAIN",
+      "archive": false
+    },
+    {
+      "tag": "FICQ-8118.RESET",
+      "addr": 30882,
+      "write_addr": 30882,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RESET",
+      "archive": false
+    },
+    {
+      "tag": "FICQ-8118.RATE",
+      "addr": 30884,
+      "write_addr": 30884,
+      "count": 2,
+      "type": "float32",
+      "access": "RW",
+      "description": "AnalogPoint aux RATE",
+      "archive": false
+    },
     {
       "tag": "FICQ-8118.FuzzyEnable",
       "addr": 30967,
diff --git a/docs/register-map-c4.json b/docs/register-map-c4.json
index 9bfc615..ecd192f 100644
--- a/docs/register-map-c4.json
+++ b/docs/register-map-c4.json
@@ -1,6 +1,6 @@
 {
   "controller": "C4",
-  "report_generated": "2026-06-18",
+  "report_generated": "2026-06-19",
   "float_format": "FP_B",
   "notes": "Register map built from Sinam_Tag_all.xlsx (C4 only). Experion point names are keys; .MD reads LoopStatus(0xBE) and writes AutoManState(0xBA). archive flag indicates history target.",
   "register_count": 2114,
diff --git a/scripts/build_register_map_from_sinam.py b/scripts/build_register_map_from_sinam.py
index 6b4276e..2fe13cf 100644
--- a/scripts/build_register_map_from_sinam.py
+++ b/scripts/build_register_map_from_sinam.py
@@ -467,6 +467,7 @@ def build_registers(sinam_path: Path, controller: str,
         sp_src = gv(row, 'SourceAddressSP')
         op_src = gv(row, 'SourceAddressOP')
         md_src = gv(row, 'SourceAddressMD')
+        is_analog = (cls == 'AnalogPoint')
 
         # 루프 판정 + mnemonic 수집은 행의 모든 셀을 스캔(scan_point)한다. GAIN1/RESET1/
         # RATE1 등 SourceAddressPV/SP/OP/MD 외 컬럼에 흩어진 파라미터까지 포착해 doc 5.2
@@ -485,7 +486,6 @@ def build_registers(sinam_path: Path, controller: str,
             # 신호/상태 포인트: PV=bare(태그명 자체), SP/OP/MD=suffix 엔트리.
             # 빈칸이면 생성 안 함, 주소가 있으면 생성(빈칸/주소 판정은 소스 컬럼 유무).
             produced = False
-            is_analog = (cls == 'AnalogPoint')
             if pv_src:
                 r = resolve_one(pv_src, controller_num)
                 if r:
@@ -516,29 +516,30 @@ def build_registers(sinam_path: Path, controller: str,
                           r['type'], access, f'{cls} {attr}', is_analog)
                 produced = True
 
-            # 보조 파라미터 A1~A4: FIQ 류 적산기는 QV(적산)가 FlexibleParameter가 아니라
-            # AnalogPoint 보조슬롯(AuxiliaryNameA{n}=QV ↔ SourceAddressA{n})에 노출된다.
-            # FICQ 류(QV=FlexibleParameter)와 달리 빌더가 놓쳤던 부분. QV=연속 누적값→archive.
-            if is_analog:
-                for n in (1, 2, 3, 4):
-                    aux_name = gv(row, f'AuxiliaryNameA{n}')
-                    aux_src  = gv(row, f'SourceAddressA{n}')
-                    if not aux_name or not aux_src:
-                        continue
-                    r = resolve_one(aux_src, controller_num)
-                    if not r:
-                        continue
-                    dst = gv(row, f'DestinationAddressA{n}')
-                    access = 'RW' if dst else r['access']
-                    write_addr = r['addr']
-                    if dst:
-                        dres = resolve_one(dst, controller_num)
-                        if dres:
-                            write_addr = dres['addr']
-                    aux_archive = (aux_name.upper() == 'QV')
-                    add_entry(f'{item_name}.{aux_name}', r['addr'], write_addr, r['count'],
-                              r['type'], access, f'{cls} aux {aux_name}', aux_archive, realtime=False)
-                    produced = True
+        # ── 보조 파라미터 A1~A4 (모든 AnalogPoint, 루프 포함) ──────────────────────
+        # FIQ 류 적산기는 QV(적산)가 FlexibleParameter가 아니라 AnalogPoint 보조슬롯
+        # (AuxiliaryNameA{n} ↔ SourceAddressA{n})에 노출된다. 슬롯명이 있는 A1~A4를
+        # 일반적으로 모두 어드레싱(공백 슬롯만 제외). 루프 엔트리와 겹치면 seen_tags가
+        # 중복을 흡수. QV=연속 누적값→archive. 보조도 폴링 대상(realtime 기본 True).
+        if is_analog:
+            for n in (1, 2, 3, 4):
+                aux_name = gv(row, f'AuxiliaryNameA{n}')
+                aux_src  = gv(row, f'SourceAddressA{n}')
+                if not aux_name or not aux_src:        # 공백 슬롯 제외
+                    continue
+                r = resolve_one(aux_src, controller_num)
+                if not r:
+                    continue
+                dst = gv(row, f'DestinationAddressA{n}')
+                access = 'RW' if dst else r['access']
+                write_addr = r['addr']
+                if dst:
+                    dres = resolve_one(dst, controller_num)
+                    if dres:
+                        write_addr = dres['addr']
+                add_entry(f'{item_name}.{aux_name}', r['addr'], write_addr, r['count'],
+                          r['type'], access, f'{cls} aux {aux_name}', aux_name.upper() == 'QV')
+                produced = True
 
         # 베이스 태그 메타데이터 (이 컨트롤러에 속해 엔트리가 생성된 경우 1회)
         if produced and db_conn and item_name not in meta_upserted: