diff --git a/scripts/build_register_map_from_sinam.py b/scripts/build_register_map_from_sinam.py
index 78704a8..6b4276e 100644
--- a/scripts/build_register_map_from_sinam.py
+++ b/scripts/build_register_map_from_sinam.py
@@ -516,6 +516,30 @@ def build_registers(sinam_path: Path, controller: str,
                           r['type'], access, f'{cls} {attr}', is_analog)
                 produced = True
 
+            # 보조 파라미터 A1~A4: FIQ 류 적산기는 QV(적산)가 FlexibleParameter가 아니라
+            # AnalogPoint 보조슬롯(AuxiliaryNameA{n}=QV ↔ SourceAddressA{n})에 노출된다.
+            # FICQ 류(QV=FlexibleParameter)와 달리 빌더가 놓쳤던 부분. QV=연속 누적값→archive.
+            if is_analog:
+                for n in (1, 2, 3, 4):
+                    aux_name = gv(row, f'AuxiliaryNameA{n}')
+                    aux_src  = gv(row, f'SourceAddressA{n}')
+                    if not aux_name or not aux_src:
+                        continue
+                    r = resolve_one(aux_src, controller_num)
+                    if not r:
+                        continue
+                    dst = gv(row, f'DestinationAddressA{n}')
+                    access = 'RW' if dst else r['access']
+                    write_addr = r['addr']
+                    if dst:
+                        dres = resolve_one(dst, controller_num)
+                        if dres:
+                            write_addr = dres['addr']
+                    aux_archive = (aux_name.upper() == 'QV')
+                    add_entry(f'{item_name}.{aux_name}', r['addr'], write_addr, r['count'],
+                              r['type'], access, f'{cls} aux {aux_name}', aux_archive, realtime=False)
+                    produced = True
+
         # 베이스 태그 메타데이터 (이 컨트롤러에 속해 엔트리가 생성된 경우 1회)
         if produced and db_conn and item_name not in meta_upserted:
             meta_upserted.add(item_name)